1. Field of the Invention
The present invention relates in general to a method for initialization of electronic circuit units which are arranged in a circuit apparatus, and to a corresponding circuit apparatus for carrying out the method, and relates in particular to a method which provides initialization of electronic circuit units while avoiding faults resulting from reference voltages which are not present.
2. Description of the Prior Art
Electronic circuit units, such as an SDRAM module, must not accept any commands during initialization until a so-called reference voltage is applied, with which an input signal is compared, for example for digitization purposes. According to the JEDEC specification (JESD 79 D), initialization of, for example, a DDR-SDRAM module must satisfy particular predetermined conditions. These include in particular “power-up” and initialization such that undefined operation is avoided.
Furthermore, from the initialization viewpoint, it is not expedient to permit a typical total time period of 10 milliseconds (ms) in accordance with the abovementioned specification for initialization. For future generations of electronic circuit units such as these, time periods such as these are longer and it must be considered, furthermore, that the various voltages, such as the operating voltage VDD and the reference voltage Vref are provided by the use of different power supply units, rather than by supplying them from a single, common voltage source.
The signals at the inputs of the electronic circuit unit, which is in the form of an SDRAM, are normally related to the reference voltage Vref that is supplied. During initialization, that is to say while Vref is still zero and until Vref has reached its final value, with the operating voltage VDD being applied, noise signals at the command inputs (instruction inputs) can disadvantageously lead to noise signals such as these being interpreted by the electronic circuit unit as command signals (instruction signals), and can thus result in a malfunction of the electronic circuit unit in a manner which is not expedient. A further disadvantage is that, in principle, a plurality of command sequences (instruction sequences) can be carried out in the abovementioned initialization time of 10 milliseconds (ms).
According to the stipulations in the JEDEC specification mentioned above, the input signals must, however, be ignored during initialization of the electronic module (of the electronic circuit unit) until the predetermined reference voltage Vref is applied.
In particular, it is not expedient for undefined instruction sequences at the input of the electronic circuit unit or noise signals which are applied to the input of the electronic circuit unit during an initialization mode to be able to lead to the electronic circuit unit (for example the SDRAM module) being unintentionally set to a test mode which changes the function of the electronic circuit unit, for example the function of the memory unit. Another problem is that, during an initialization phase, it is possible for driver devices to cause a short circuit on the board as a result of the provision of output signals from the electronic circuit unit, which are passed on to the driver devices.
FIG. 2 shows a conventional electronic circuit apparatus which, for example, comprises three electronic circuit units. The electronic circuit units which are illustrated in FIG. 2 are referred to as an OCD (OCD=off-chip driver, output driver), a receiver, which corresponds to a receiving unit, and a decoder. When input signals are supplied to an electronic circuit unit, for example in the central electronic circuit unit (“receiver”), then these input signals Vin are supplied to an input signal connection E.
The input signals Vin are evaluated in the receiver with respect to a reference signal Vref which is supplied to a reference signal connection V. The output signal Vout which is emitted from an output signal connection A is emitted from the electronic circuit unit, that is to say the output driver (“OCD”) as a function of the input and reference signals Vin and Vref, respectively, which are supplied. In the circuit arrangement that is illustrated in FIG. 2, the major disadvantage is that the reference voltage Vref is applied continuously via the reference signal connection V, that is to say even during an initialization phase of the circuit apparatus which comprises the three circuit units OCD, receiver and decoder. This leads in a manner which is not expedient to the possibility of noise signals at an input connection E, for example of the central electronic circuit unit, being able to switch this to an operating mode that is not permissible.